New PDF release: Beyond CMOS Nanodevices 2

By Francis Balestra

ISBN-10: 1848216556

ISBN-13: 9781848216556

This ebook deals a entire evaluation of the state of the art in leading edge Beyond-CMOS nanodevices for constructing novel functionalities, good judgment and stories devoted to researchers, engineers and scholars. The ebook will quite specialise in the curiosity of nanostructures and nanodevices (nanowires, small slope switches, second layers, nanostructured fabrics, etc.) for complex greater than Moore (RF-nanosensors-energy harvesters, on-chip digital cooling, etc.) and Beyond-CMOS good judgment and thoughts functions.

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The increase of uniaxial compressive strain in the channel coming from the use of recessed S/D SiGe stressors may be a promising option for SOI NW technology. 15. 15. 8 nA/µm). The NW width is also expected to have a large impact on performance due to the change of mobility in <110> NWs. By reducing the NW width, a large mobility improvement induced by a significant increase of subband curvature and hole velocity is expected [NEO 10]. 16(a). The results show a major improvement of the saturation current, from +40% for wide planar transistors up to +100% for narrow NW transistors.

17. Currents and electron densities are normalized with respect to the effective width Weff = 4WNW = 4T for NWs and Weff = 2WDG for DGs. This choice assures a similar dependence on the gate overdrive of the transfer characteristics of the two geometries under study. The effect of the SR on the current is qualitatively known from previous results in the literature [BUR 09]. It consists in a positive threshold-voltage shift ΔVT and a current reduction at large overdrives. However, due to the larger fluctuations of the first subband of the unprimed valley induced by the rough interfaces, ΔVT turns out to be larger in NWs than in DGs.

Perspectives of low power VLSI’s”, IEICE Trans. , vol. E87-C, pp. 429–436, April 2004. , “Use of negative capacitance to provide voltage amplification for low power nanoscale devices”, Nanoletters, vol. 8, no. 2, pp. 405—410, 2008. , “Demonstration of subthrehold swing smaller than 60mV/decade in Fe-FET with P(VDFTrFE)/SiO2 gate stack”, 2008 IEDM Tech. , Electron Devices Meeting, pp. 1–4, 2008. , BOUVET D. , “Ferroelectric transistors with improved characteristics at high temperature”, Applied Physics Letters, vol.

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Beyond CMOS Nanodevices 2 by Francis Balestra


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