Digital Phase Lock Loops by Saleh R. Al-Araji PDF

By Saleh R. Al-Araji

ISBN-10: 1441941053

ISBN-13: 9781441941053

This interesting new ebook covers numerous kinds of electronic part lock loops. It offers a complete insurance of a brand new classification of electronic part lock loops known as the time hold up tanlock loop (TDTL). It additionally information a few architectures that increase the functionality of the TDTL via adaptive options that triumph over the conflicting requisites of the locking rage and pace of acquisition.

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Extra resources for Digital Phase Lock Loops

Example text

The main parts in each class are clarified. It has been shown that the most important kind of DPLLs is the nonuniform sampling sinusoidal zero-crossing DPLL (ZC-DPLL). Hence we will concentrate on this kind of DPLLs in this book. Developments in this respect are presented. Two major approaches exist in this field: the original approach of sinusoidal DPLL built on fixed point analysis and the approach of tanlock phase detection. In this book we will present a combination of the above two approaches that will give many advantages over the existing types of DPLLs.

A. Locking Conditions In the steady-state we have φ(k+2) = φ(k+1) = φ(k), hence e(k+1) = e(k). Therefore, the steady-state value of the output of the phase detector ess is zero. 13) it is evident that the steady-state phase error φss is nπ (n being an integer). Since f [φss ] = ±π we must have f [φss ] = 0, hence φss = 2mπ (m being an integer). 44 CHAPTER 3 Following the same fixed point analysis as that given by Osborne [51], the locking conditions can be obtained from the condition that the eigenvalues of the matrix G given by G= 0 1 −1 + K1 csc(ψ) 2 − rK1 csc(ψ) must be less than 1.

The ranges of independent locking for CDTL and TDTLs are the areas enclosed by the dashed line and the appropriate curves. and that the other limits, lim hψ (φ) and lim hψ (φ), are not considered as they φ→π + φ→−π − are outside the interval (−π, π). It is worth noting that the above two conditions are independent of ψo . 2 for the second-order CDTL and TDTL with different values of ψo . 4 Locking Speed In this section, the convergence behavior of the TDTL in the absence of noise is analyzed. This analysis concentrates on the actual number of steps necessary for convergence of the phase error to within a radius of the steady-state phase error.

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Digital Phase Lock Loops by Saleh R. Al-Araji


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