By Zhiheng Cao, Shouli Yan
Low-Power High-Speed ADCs for Nanometer CMOS Integration is concerning the layout and implementation of ADC in nanometer CMOS techniques that in achieving decrease energy intake for a given pace and backbone than past designs, via architectural and circuit recommendations that make the most of detailed positive factors of nanometer CMOS tactics. A section lock loop (PLL) clock multiplier has additionally been designed utilizing new circuit recommendations and effectively proven. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. utilizing offset canceling comparators and capacitor networks applied with small worth interconnect capacitors to exchange resistor ladder/multiplexer in traditional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz enter. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz inner clock in 130nm CMOS. a brand new form of structure that mixes flash and SAR allows the bottom strength intake, 6-bit >1GS/s ADC said up to now. This layout could be a drop-in alternative for current flash ADCs because it does require any post-processing or calibration step and has a similar latency as flash. three) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for producing sampling clock to the SAR ADC. a brand new loop filter out constitution allows part errors preamplification to decrease PLL in-band noise with out expanding loop clear out capacitor dimension.
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Additional resources for Low-Power High-Speed ADCs for Nanometer CMOS Integration (Analog Circuits and Signal Processing)
3 Enabling Circuits 53 M5 Dout M4 M3 latch latch latch M2 Vin+ Vin− M1 latch Fig. 5 GHz low hysteresis comparator Because of the way the ﬂip-ﬂop bypass SA logic works, the comparator must hold the decision until the next latch edge, therefore a slave latch, typically realized by cross-coupled NAND gate for this type of comparator, must be used. The outputs of the master dynamic comparator that goes directly to the slave latch were connected to the bottom NMOS rather than top NMOS that is exposed to NAND gate outputs.
As a result, half clock cycle is allowed for the CADC latch to regenerate and the binary encoder to settle. As shown later in experimental results, there has been a critical mistake in this design not to put a latch stage at the output of the CADC binary encoder which is opaque when Φ1 is high and transparent when Φ1 goes low. ) This mistake prevented the ADC to achieve sufﬁcient performance for > −40 dBFS input (when the CADC output starts to toggle) at 300 MS/s, which is the sampling speed for which the ADC was originally designed.
The very small load on the ladder not only speeds up its settling but also reduces long-term / DC error generated by bowing due to static current drawn from the ladder. 6 mA (each section is 27 Ω), much less current than those in conventional subranging ADCs that drive FADC, for example 15 mA is used in . Since the input of the offset canceling comparator is reset to vicm each time, and subsequently driven up to Vre f [n] − vin, there is a ﬁnite amount of DC current drawn from the nth reference point of the ladder, which can be approximated as (Vre f [n] − vin − vicm) fs (Cgs + Cgd ), where fs is the ADC sampling frequency (designed for 300 MHz).
Low-Power High-Speed ADCs for Nanometer CMOS Integration (Analog Circuits and Signal Processing) by Zhiheng Cao, Shouli Yan